FIGS. 3(a) through 4(b) show cross-sectional views in a prior art production process of a multi-layer wiring. In these figures, reference numeral 1 designates a semiconductor substrate on a prescribed region of which semiconductor elements such as FETs, which are not shown here, are formed. First kind layer wirings 2a and 2b on the semiconductor substrate 1 are, for example, electrodes of the FETs. An insulating film 3 is formed covering the first kind layer wirings 2a and 2b on the semiconductor substrate 1 as an inter-layer insulating film. A second kind layer wiring 4 is, for example, a power supply line, and this second kind layer wiring 4 is formed by patterning the second kind layer wiring layer 4a. A photoresist pattern 5 is used as a mask when the second kind layer wiring layer 4a is patterned to a prescribed pattern. A photoresist 6 is used for separating the lower layer wiring and the upper layer wiring When producing an airbridge structure. A gilding feeding layer 7 is provided so as to supply an electric current for plating. A resist pattern 8 is provided as a mask when producing a third kind layer wiring 9. This third kind layer wiring 9 is produced by gilding, and functions, for example, as a signal line. Reference numeral 8a designates an aperture of the resist pattern 8. Here, the first kind layer wiring 2a, 2b, the second kind layer wiring 4, and the third kind layer wiring 9 are formed by different processes, and used as wirings for different functions.
A description is given of the production process of the multi-layer wiring with reference to FIGS. 3(a) through 4(b).
After forming the first kind layer wirings 2a, 2b at prescribed regions at the surface of the semiconductor substrate 1, an insulating film 3 is formed on the entire surface of the semiconductor substrate 1 covering the first kind layer wirings 2a and 2b. Thereafter, the wiring metal layer 4a comprising such as a lamination of Ti/Au, is deposited on the entire surface of the insulating film 3 by sputtering, and thereafter, a resist pattern 5 is formed at a prescribed region of the metal layer lamination 4a, thereby resulting the state of FIG. 3(a).
Next, the wiring layer metal layer 4a is patterned by ion milling employing the resist pattern 5 as a mask, thereby producing a second kind layer wiring 4, and thereafter, the resist pattern 5 is removed, resulting in the state shown in FIG. 3(b).
Next, a resist 6 is deposited covering the second kind layer wiring 4 and the insulating film 3, and thereafter, a gilding feeding layer 7 comprising, for example, a lamination of Ti/Au is deposited on the entire surface of the resist 6, and further, a resist pattern 8 is produced at the surface of the gilding feeding layer 7, resulting in the state shown in FIG. 3(c).
Next, as shown in FIG. 4(a), the resist pattern 8 is employed as a mask for electrolytic plating, thereby forming a third kind layer wiring 9 comprising, for example, Au at the aperture 8a of the-resist pattern 8.
Next, after the resist pattern 8 is removed, the gilding feeding layer 7 is removed by ion milling, and further the resist 6 is removed, thereby resulting a multi-layer wiring in which the first kind layer wiring 2 and the second kind layer wiring 4 are separated by the insulating film 3 and the second kind layer wiring 4 and the third kind layer wiring 9 are separated in the airbridge structure. Although only one second kind layer wiring and one third kind layer wiring are illustrated, and only one crossing part of the wirings is illustrated here, the second kind layer wiring and the third kind layer wiring are usually formed in plurality since the first kind layer wiring, and the crossing part of the second kind layer wiring and the third kind layer wiring and the crossing part of the first kind layer wiring and the second kind layer wiring are formed in plurality.
The multi-layer wiring of the prior art semiconductor device is produced as described above, and it is possible to construct the crossing part of the second kind layer wiring and the third kind layer wiring in an airbridge structure, and thereby it is possible to significantly reduce the inter-wiring capacitance between these two wirings. However, because the crossing part of the first kind layer wiring and the second kind layer wiring on the semiconductor substrate is separated only by the insulating film between these two wirings, it was impossible to sufficiently reduce the inter-layer capacitance.